1. Field of the Invention
The present invention relates to a digital memory circuit and, more particularly, to a video digital memory color framing circuit for an NTSC color television signal modulated by pulse code modulation (PCM) based on composite coding system.
2. Description of the Prior Art
A conventional video memory color framing circuit will be explained by way of frame synchronizer. Referring to FIG. 1, an input analog television signal 1 is supplied to an A/D converter 2. The A/D converter 2 samples the input television signal at a sampling frequency of 14.3 MHz which is four times the color subcarrier frequency. The input television signal 1 is thus converted by the A/D converter 2 to a PCM parallel n-bit data 3 (where n=9). The input television signal 1 is also supplied to a write clock generator 12 comprising a burst controlled oscillator (BCO). The write clock generator 12 comprises a phase comparator 6, an oscillator 8 oscillating at a frequency four times a burst frequency F.sub.SC of the input television signal 1, and a 1/4 frequency division counter 10. The write clock generator 12 then generates a write clock pulse 9 in synchronism with the color burst. The input television video signal 1 is also supplied to a horizontal (H) pulse separator 13 and a vertical (V) pulse separator 17. The horizontal pulse separator 13 then generates a horizontal pulse 14 having the horizontal period, whereas the vertical pulse separator 17 produces a separated vertical pulse and a vertical pulse 18 having the vertical period, which latter is obtained by delaying the separated vertical pulse. The horizontal pulse 14 is supplied to a burst flag generator 15 which then generates a burst flag pulse 16. It is noted that in the NTSC color television signal, the relations among a frequency F.sub.SC of a color subcarrier 11, a horizontal pulse frequency F.sub.H, and a separated vertical pulse frequency F.sub.V are defined as F.sub.SC =455/2F.sub.H and F.sub.H =525/2F.sub.V. The phase relation "SCH timing" between the color subcarrier and the horizontal sync signal, which complies with standard RS-170 A of the EIA, and relations among color fields I to IV are shown at sections (a), (e), (f), (a'), (e' ) and (f') in FIG. 3. In the figure, H reprensents one period of the horizontal sync pulse and subcarrier phases are depicted at the timing of start of horizontal scanning.
A detection window pulse is produced by a delay multivibrator triggered by the horizontal pulse 14, so that a zero-crossing positive edge pulse of the subcarrier 11 synchronous with the burst of the input television signal 1 is detected by an SCH detector 19. The horizontal pulse 14 and a detection signal 20 from the SCH detector 19 are supplied to a write line flip-flop generator 21. The write line flip-flop generator 21 generates a write line flip-flop pulse (to be referred to as a WLFF.sub.0 pulse) 22 having a 1/2 horizontal sync signal frequency (F.sub.H /2) and being in synchronism with the SCH phase relation of the subcarrier 11 synchronous with the color burst. The WLFF.sub.0 pulse 22 is supplied as a color flag pulse to a color flag mixer 4. The color flag pulse is used to detect which one of the color fields I to IV corresponds to a color field in the 8th TV (horizontal scanning) line in the vertical blanking period during which the vertical pulses 18 are generated. It is noted that the 8th line corresponds to a first line of the vertical address. The color flag mixer 4 then mixes the WLFF.sub.0 pulse and a digital signal from the A/D converter 2, and produces a PCM data 5 such that the WLFF.sub.0 pulse is inserted in the MSB (most significant bit) of the PCM data 5. Meanwhile, a write odd/even field detection signal is produced from the horizontal pulse 14 and the separated vertical pulse. The write odd/even field detection signal, the horizontal pulse 14, the vertical pulse 18, the subcarrier 11, and the write clock pulse 9 are supplied to a write address counter 23, which then produces a write address signal 24. The write address counter 23 comprises a vertical address counter for counting the number of horizontal pulses 14 during a one-field period, and a horizontal address counter for counting the number of subcarriers 11 during one horizontal scanning period. The operation sequence of the write address counter 23 is exemplified as a modification of the NTSC color TV standard in FIG. 4. When the WLFF.sub.0 pulse is kept low, the number of subcarriers during one horizontal scanning period is 228. However, when the WLFF.sub.0 pulse goes high, the number of subcarriers is 227.
The phase of a first subcarrier of each write horizontal address signal with respect to the phase of the horizontal pulse phase (start of horizontal scanning or left end of screen), that is, the phase of a horizontal clear pulse of the write address counter, is indicated by a solid dot (.cndot.) at (a) in FIG. 5. In the figure, symbols .circle. , .circleincircle. , .DELTA. and .DELTA. denote a start phase of a frame. The PCM data 5 having the color flag signal in its MSB is stored in a memory cell of a one-frame memory 30 accessed by the write address signal 24.
Meanwhile, in the same manner as in the write circuit arrangement, a reference timing signal (a black burst signal or a video signal VBS) 1' is supplied to a read clock generator 12' and a read address generator 25'. The read clock generator 12' generates a read clock pulse 9' and a subcarrier pulse 11'. A read address generator 25' generates a horizontal pulse 14', a vertical pulse 18', a read odd/even field detection signal, and a first read line flip-flop pulse (to be referred to as an RLFF.sub.0 pulse) 22'. In order to detect which one of the color fields I to IV corresponds to the written color field, the polarity of bit 38 (color flag signal) of PCM data 31 read out from the one-frame memory 30 is loaded in a second read line flip-flop generator 21" in synchronism with the phase of the vertical pulse 18' at the 8th line in the vertical blanking period of the reference timing signal 1', as shown at (a') and (h') in FIG. 3. To this end, the PCM data 31 is read out from the one-frame memory 30 by a read address signal 24', performing odd/even field detection, and assigning the vertical address of each field to the first line (1) (see sections (c) and (c') in FIG. 3).
After the polarity of the color flag signal is loaded in the second read line flip-flop generator 21", the horizontal pulse 14' is used as a clock pulse for the second read line flip-flop generator 21" in the form of a toggle flip-flop. The second read line flip-flop generator 21" then generates a second read line flip-flop pulse (to be referred to as an RLFF.sub.1 pulse hereinafter) 22". The RLFF.sub.1 pulse 22" thus has a frequency corresponding to 1/2 the horizontal sync pulse frequency (F.sub.H /2), indicating the relationship between the phase of the horizontal pulse 14' of the one-field period data to be read out from the one-frame memory 30 and the phase of the first PCM video data 31 of the one horizontal scanning period. The first phase of the video data 5 which is written in the one-frame memory 30 in the horizontal scanning period with respect to the phase of the horizontal pulse 14 is indicated by the black dot (.cndot.) at (a) in FIG. 5. As may be apparent from the output video signal phases as indicated by black dots in Cases 1, 2-1 and 2-2, when the first phase of the video data in the horizontal scanning period is shifted with respect to the phase of the horizontal pulse 14', one-field (and one-frame) video data 31 can be read out from the one-frame memory 30 without modifying the output video signal phase of each line to an inverted zigzag pattern. The first phase described above corresponds to the phase of the horizontal clear pulse of the read address signal 24' from the read horizontal address counter. The above phase-shift operation can be thus performed in the same manner as in change of the polarity of the RLFF.sub.1 pulse 22", that is, as in change of the write phase as indicated by the black dots at (a) in FIG. 5. The video data 31 is then mixed with the digital blanking signal and the digital burst signal. This composite digital signal is then supplied to a D/A converter 36. The D/A converter thus reproduces an analog television signal 37.
However, in the conventional circuit, as shown in Cases 1, 2-1 and 2-2 at (b) in FIG. 5, the phase of the output video signal 31 (35 or 37) is offset from the phase of the horizontal pulse 14' by 0, -0.5 SC (-140 nsec), and +0.5 SC (+140 nsec). Furthermore, since the digital burst signal and the digital blanking signal (synchronous with the color fields I to IV of the reference timing signal 1') are controlled only by the RLFF.sub.0 pulse 22' and are mixed with the video data in a PROM (programmable read-only memory), independently of the RLFF.sub.1 pulse 22" from the second read line flip-flop 21", a blanking burst address generator 39 must be arranged in the read address generator 25' in addition to a read address counter 23'.
A reason for the output video phase offset (0, -0.5 SC and +0.5 SC) in the conventional circuit will be described in detail hereinafter. In the NTSC standard, the phase of a color subcarrier for a preceding frame is shifted by 180.degree. from the phase of the color subcarrier for a succeeding frame. The phase relation between the color subcarrier and the horizontal sync signal, therefore, recur at a 4-field cycle. Therefore, four fields are set as a so-called color frame. When the capacity of the memory of the frame synchronizer corresponds to a one-frame capacity, the phases of the color frames in the write and read systems are asynchronous. When the color fields I and II shown at (a) in FIG. 5 are written and then read out, the reference timing signal 1' corresponds to the color fields I and II (Case 1 at (b) in FIG. 5) or to the color fields III and IV (Case 2 at (b) in FIG. 5). The relationships among the phases (H phase) of the horizontal pulses 14 and 14', the phases (indicated by one sinusoidal wave (.about. )) of the subcarriers 11 and 11', and the phases (indicated by a combination of a black dot and one sinusoidal wave) of the horizontal clear signal from the horizontal address counter with respect to the number of subcarriers in one line (228 when the WLFF.sub.0 is low; 227 when the WLFF.sub.0 is high) in Case 1 will be described with reference to FIGS. 5 and 6.
In this example, the phases of the read and write horizontal clear signals are controlled by the horizontal address counter in unit of one subcarrier period in order to prevent color inversion of the output video signal in the transient periods of the mutual overrun of the read and write color frames, as shown in FIGS. 5 and 6. Consequently, the horizontal clear pulse phase with respect to the horizontal pulse phase has a zigzag pattern. If the number of subcarriers in one line of the write horizontal address counter is 228 (when the WLFF.sub.0 is low), the horizontal clear pulse phase is the same as the phase of the horizontal pulse 14. In this case, the horizontal address counter counts 228 subcarriers, so that the horizontal addresses are "0" to "227". When the horizontal address counter counts the 228th subcarrier, the horizontal address is the address "227". In this condition, the address decoder generates the clear pulse ((f) in Case 1 of FIG. 6) to clear the horizontal addresses when the horizontal address counter counts the next subcarrier. When the number of subcarriers is 227 (when the WLFF.sub.0 is high), the horizontal address counter counts 227 subcarriers, so that the horizontal addresses are "0" to "226". When the horizontal address counter counts the 227th subcarrier, the horizontal address corresponds to the address "226", and it generates a clear pulse ((g) in Case 1 of FIG. 6). Therefore, the WLFF.sub.0 pulse controls the timing for generating the clear pulse at the address decoder. In Case 1, the written color field I is read out as the color field I, so that the number of subcarriers in the first scanning line is 228 (when WLFF.sub.0 is low), and so that the number of subcarriers in the first scanning line for the read color field I is 228 (when RLFF.sub.0 and RLFF.sub.1 are both low). Therefore, as shown in Case 1 in FIG. 6, the horizontal clear pulses have phases which correspond to those of the reference horizontal pulses 14 and 14', so that the output video signal phase offset is 0.
Case 2 will be described in which the written color field I is read out as the color field III of the reference timing signal 1'. The number of subcarriers in the first scanning line of the written color field I is 228 (the WLFF.sub.0 is low). However, the number of subcarriers of the read color field III is 227 (the RLFF.sub.0 is high with respect to the phase of the horizontal pulse 14' of Case 2 in FIG. 5(b)). In order to satisfy the read reference color frame, the output video signal must be horizontally shifted by -0.5 SC (in Case 2-1) or +0.5 SC (in Case 2-2) instead of inverting its phase by 180.degree.. Case 2-1 in FIG. 5 will be described with reference to Case 2-1 in FIG. 6. After the relation between the write and read color frames set forth thus far had been in Case 1, Case 2 in a transient period will be described wherein the input television signal 1 has changed so as not to synchronize with the previous input television signal. Even if the read horizontal address counter is predicted generate the horizontal clear pulse at the timing of the horizontal address "227" as if in (f) of Case 1 in FIG. 6 on the assumption that a new color flag signal read out from the one-frame memory 30 is high (when RLFF.sub.0 is low), the RLFF.sub.1 goes to high and the horizontal decoder generates the clear pulse at the address "226". As a result, the output video phase advances by -0.5 SC.
Case 2-2 in FIG. 5 will be described with reference to Case 2-2 in FIG. 6. Similarly, after the relation between the write and read color frames set forth thus far had been in Case 1, Case 2 in a transient period will be described wherein the input television signal 1 has changed so as not to synchronize with the previous input television signal. Even if the read horizontal address counter is predicted to generate the horizontal clear pulse at timing of the horizontal address "226" as if in (e) of Case 1 in FIG. 6 on the assumption that a new color flag signal read out from the one-frame memory 30 is low (when RLFF.sub.0 is high), low and the horizontal decoder generates the horizontal clear pulse at the address "227". As a result, the output video phase is lagged by +0.5 SC.
The write horizontal pulse 14 is used as the clock pulse for the write line flip-flop generator 21, and the read horizontal pulse 14' is used as the clock pulse for the first and second read line flip-flop generators 21' and 21" for illustrative convenience in FIGS. 1 and 2. However, in practice, in order to assure the control timing of the line flip-flop pulses at the horizontal clear pulse timing of the horizontal address, delayed write and read sync pulses which are delayed by about 1/2 H scanning period are respectively used as the write and read horizontal pulses.
In fine, the conventional circuit has drawbacks as follows:
(1) The output video signal phase offset from the horizontal pulse is 0, -140 nsec, and +140 nsec (280 nsec in peak-to-peak value).
(2) The blanking/burst address generator 39 is necessary in addition to the read address counter 23'.